A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

A parallel - pipelined A/D converter with an area and power efficient architecture is described, By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture), By using two such pipelines in parallel, a 52 M samples/s prototype A/D converter that is intended for a su itched digital video application has been implemented in a 0.9-mu m CMOS technology, The device occupies 15 mm(2) and dissipates 250 mW from a 5 V supply.