The circuit andphysical design of the POWER4 microprocessor

被引:73
作者
Warnock, JD
Keaty, JM
Petrovick, J
Clabes, JG
Kircher, CJ
Krauter, BL
Restle, PJ
Zoric, BA
Anderson, CJ
机构
[1] IBM Corp, Div Res, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] IBM Corp, Microelect Div, Austin, TX 78758 USA
[3] IBM Corp, Enterprise Syst Grp, Austin, TX 78758 USA
关键词
D O I
10.1147/rd.461.0027
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The IBM POWER4 processor is a 174-million-transistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.
引用
收藏
页码:27 / 51
页数:25
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