Electrical properties of nonvolatile latches for new logic application

被引:6
作者
Fujimori, Y [1 ]
Nakamura, T [1 ]
Takasu, H [1 ]
机构
[1] ROHM Co Ltd, Semicond R&D Headquarters, Ukyo Ku, Kyoto 6158585, Japan
关键词
D O I
10.1080/10584580215414
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel nonvolatile latch with ferroelectric capacitors has been developed to reduce standby power of LSIs. This latch stores the data as a ferroelectric remanent polarization during power off without area penalty and operating speed degradation. Test circuits have been fabricated to confirm characteristics of the latch. The data retention and the stable recall procedure have been confirmed. This paper also describes scaling projection of this technique.
引用
收藏
页码:71 / 78
页数:8
相关论文
共 6 条
[1]  
KIJIMA T, 2001, FERAM 2001 GOT JAP N, P67
[2]  
Kumagai K., 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), P44, DOI 10.1109/VLSIC.1998.687998
[3]   A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM [J].
Miwa, T ;
Yamada, J ;
Koike, H ;
Nakura, T ;
Kobayashi, S ;
Kasai, N ;
Toyoshima, H .
2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, :129-132
[4]   1-V POWER-SUPPLY HIGH-SPEED DIGITAL CIRCUIT TECHNOLOGY WITH MULTITHRESHOLD-VOLTAGE CMOS [J].
MUTOH, S ;
DOUSEKI, T ;
MATSUYA, Y ;
AOKI, T ;
SHIGEMATSU, S ;
YAMADA, J .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (08) :847-854
[5]  
NISHIHARA T, 2001, ISSCC SAN FRANC FEB, P160
[6]   A 0.9-μA standby current DSP core using improved ABC-MT-CMOS with charge pump circuit [J].
Notani, H ;
Koyama, M ;
Mano, R ;
Makino, H ;
Matsuda, Y .
2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, :221-224