Experimental and analytical study of seed layer resistance for copper damascene electroplating

Copper electroplating for integrated circuit damascene applications typically relies on a thin, conductive seed layer to promote nucleation of feature fill and acceptable overall thickness distribution during deposition. Important to the charge-transfer exchange process occurring at the wafer surface is the potential drop within the seed layer during the early stages of plating. The effective damascene surface area, seed layer coverage, and overall resistance of thin Cu films are examined via modeling and experimental measurements. The current-carrying capability of seed-metallized trenches is calculated in terms of an effective trench resistivity and used to compare physical vapor deposition (PVD) methods with chemical vapor deposition (CVD). For a nominal 2:1 aspect ratio trench, the modeled CVD seed resistance was found to be 5X lower than that of ionized PVD and about 2.8X lower than that of ionized PVD with resputter. Wafer-level resistance probing is introduced as a useful means to assess global differences in seed layer resistance on actual patterned substrates. Initial measurements on low-density patterns confirm that PVD seed films exhibit larger increases (+24% to 78%) in resistance than CVD films (+11%) when compared to their respective planar counterparts. Results indicate that seed resistance levels on patterned damascene substrates can be significantly larger than on planar monitor wafers-an important implication for the Cu plating manufacturing process. (C) 1999 American Vacuum Society. [S0734-211X(99)03406-X].