Simulating process-induced gate oxide damage in circuits

被引：5

作者：

King, JC

Shin, H

Hu, CM

机构：

[1] KOREA ADV INST SCI & TECHNOL,TAEJON 305701,SOUTH KOREA

[2] UNIV CALIF BERKELEY,DEPT ELECT ENGN & COMP SCI,BERKELEY,CA 94720

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1997年 / 44卷 / 09期

关键词：

D O I：

10.1109/16.622593

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability, We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator.

引用

页码：1393 / 1400

页数：8

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