Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in pMOS transistors

被引：116

作者：

Huard, V ^{[1
]}

Denais, M ^{[1
]}

机构：

[1] Philips Semicond, F-38926 Crolles, France

来源：

2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/RELPHY.2004.1315299

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：40 / 45

页数：6

共 7 条

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