Electrical characteristics of ultra-fine trench isolation fabricated by a new two-step filling process

被引：4

作者：

Shiozawa, K ^{[1
]}

Oishi, T ^{[1
]}

Maeda, H ^{[1
]}

Murakami, T ^{[1
]}

Yasumura, K ^{[1
]}

Abe, Y ^{[1
]}

Tokuda, Y ^{[1
]}

机构：

[1] MITSUBISHI ELECTR CORP, ULSI LAB, ITAMI, HYOGO 664, JAPAN

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS | 1996年 / 35卷 / 12B期

关键词：

ULSI; trench isolation; breakdown voltage; narrow channel transistor;

D O I：

10.1143/JJAP.35.L1625

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

An ultra-fine trench isolation with superior electrical properties was formed using a new fabrication process. A void-free shape and sufficient thickness of the field oxide were realized by two-step filling using tetraethyl-orthosilicate (TEOS) oxide as the lower layer and high-density CVD-SiO2 as the upper capping layer. The breakdown voltages were as high as 7.7 V, even for an isolation space as narrow as 0.13 mu m. The subthreshold characteristics of the metal oxide semiconductor field effect transistor (MOSFET) isolated by the trench were kink-free. The threshold voltage of the parasitic MOSFET, furthermore, was more than 6V, even without a channel stop implant to suppress punch-through.

引用

页码：L1625 / L1627

页数：3

共 6 条

[1]

BRYANT A, 1994, 1994 INT EL DEV M DE, P671

[2] A shallow trench isolation study for 0.25/0.18 mu m CMOS technologies and beyond [J].

Chatterjee, A ;

Esquivel, J ;

Nag, S ;

Ali, I ;

Rogers, D ;

Tayor, K ;

Joyner, K ;

Mason, M ;

Mercer, D ;

Amerasekera, A ;

Houston, T ;

Chen, LC .

1996 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1996, :156-157

[3] A HALF-MICRON CMOS LOGIC GENERATION [J].

KOBURGER, CW ;

CLARK, WF ;

ADKISSON, JW ;

ADLER, E ;

BAKEMAN, PE ;

BERGENDAHL, AS ;

BOTULA, AB ;

CHANG, W ;

DAVARI, B ;

GIVENS, JH ;

HANSEN, HH ;

HOLMES, SJ ;

HORAK, DV ;

LAM, CH ;

LASKY, JB ;

LUCE, SE ;

MANN, RW ;

MILES, GL ;

NAKOS, JS ;

NOWAK, EJ ;

SHAHIDI, G ;

TAUR, Y ;

WHITE, FR ;

WORDEMAN, MR .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1995, 39 (1-2) :215-227

[4]

Lee HS, 1996, 1996 SYMPOSIUM ON VLSI TECHNOLOGY, P158, DOI 10.1109/VLSIT.1996.507832

[5]

PERERA AH, 1995, 1995 INT EL DEV M DE, P679

[6]

ROH BH, 1996, P 1996 INT C SOL STA, P830

← 1 →