An MLSE receiver for electronic dispersion compensation of OC-192 fiber links

被引:48
作者
Bae, Hyeon-Min [1 ]
Ashbrook, Jonathan B.
Park, Jinki
Shanbhag, Naresh R.
Singer, Andrew C.
Chopra, Sanjiv
机构
[1] Intersymbol Commun Inc, Champaign, IL 61820 USA
[2] Univ Illinois, Dept Elect & Comp Engn, Champaign, IL 61820 USA
关键词
A/D converter (ADC); clock data recovery (CDR); demultiplexer (DEMUX); electronic dispersion compensation (EDC); electronic post-detection equalization (EDE); G.709 optical transport network (OTN); high-speed ASIC; maximum-likelihood sequence estimation (MLSE); OC-192; phase-locked loop (PLL); variable gain amplifier (VGA);
D O I
10.1109/JSSC.2006.883317
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A maximum-likelihood sequence estimation (MLSE) receiver is fabricated to combat dispersionlintersymbol interference (chromatic and polarization mode), noise (optical and electrical), and nonlinearities (e.g., fiber, receiver photodiode, or laser) in OC-192 metro and long-haul links. The MLSE receiver includes a variable gain amplifier with 40-dB gain range and 7.5-GHz 3-dB bandwidth, a 12.5-Gb/s 4-bit analog-to-digital converter, a dispersion-tolerant phase-locked loop, a 1:8 demultiplexer, and a digital 'equalizer implementing the MLSE algorithm. The MLSE receiver achieves more than 50% reach extension at signal-to-noise levels of interest as compared to conventional clock data recovery systems.
引用
收藏
页码:2541 / 2554
页数:14
相关论文
共 20 条
[1]  
*10 GIG MSA CONS, 2001, 300 PIN MULT SOURC A
[2]   CLOCK RECOVERY FROM RANDOM BINARY SIGNALS [J].
ALEXANDER, JDH .
ELECTRONICS LETTERS, 1975, 11 (22) :541-542
[3]  
[Anonymous], 1994, DIGITAL COMMUNICATIO
[4]   A 140-MB/S, 32-STATE, RADIX-4 VITERBI DECODER [J].
BLACK, PJ ;
MENG, TH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (12) :1877-1885
[5]  
BULOW H, 2001, P OFC
[6]   A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS [J].
Choi, M ;
Abidi, AA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (12) :1847-1858
[7]  
Elbers J.P., 2005, P OFC
[8]   A 60-dB gain, 55-dB dynamic range, 10-gb/s broad-band SiGe HBT limiting amplifier [J].
Greshishchev, YM ;
Schvan, P .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (12) :1914-1920
[9]   SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application [J].
Greshishchev, YM ;
Schvan, P .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (09) :1353-1359
[10]  
HAUNTEIN HF, 2001, P OFC, P3