A very small bipolar transistor technology with sidewall polycide base electrode for ECL-CMOS LSP's

被引:6
作者
Shiba, T [1 ]
Tamaki, Y [1 ]
Onai, T [1 ]
Kiyota, Y [1 ]
Kure, T [1 ]
Nakamura, T [1 ]
机构
[1] HITACHI LTD,DEVICE DEV CTR,TOKYO 198,JAPAN
关键词
D O I
10.1109/16.535319
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Very small, high-performance, silicon bipolar transistors (SPOTEC) were developed for use in ECL-CMOS LSI's, The transistors are fabricated with a sidewall polycide base; chemical vapor deposition is used to selectively deposit tungsten on the sidewall surface of the polysilicon base, The tungsten is then silicided, This self-aligned polycide technology makes a narrow (0.4-mu m wide), low-resistance (7 Omega/square) base electrode possible, Narrow U-groove isolation and narrow collector metallization techniques are used to reduce the transistor area to 10 mu m(2). A shallow E-B junction and base layer have now been formed by using rapid-vapor-phase doping, The resulting transistors have good I-V characteristics without leakage current or high current gain, They have a high cut-off frequency of 37 GHz (53 GHz with pedestal collector ion implantation and thin epitaxial layer) and small junction capacitances, These transistors will facilitate the development of very-high-speed, high-density ULSI's.
引用
收藏
页码:1357 / 1363
页数:7
相关论文
共 13 条
[1]  
Harame D. L., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P19, DOI 10.1109/IEDM.1992.307299
[2]  
Kerber M., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P449, DOI 10.1109/IEDM.1992.307398
[3]   ULTRA-THIN-BASE SI BIPOLAR-TRANSISTOR USING RAPID VAPOR-PHASE DIRECT DOPING (RVD) [J].
KIYOTA, Y ;
ONAI, T ;
NAKAMURA, T ;
INADA, T ;
KURANOUCHI, A ;
HIRANO, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (09) :2077-2081
[4]  
KIYOTA Y, 1994, IEICE T ELECTRON, VE77C, P362
[5]  
Konaka S., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P493, DOI 10.1109/IEDM.1990.237060
[6]   AN ULTRA-HIGH-SPEED ECL-BICMOS TECHNOLOGY WITH SILICON FILLET SELF-ALIGNED CONTACTS [J].
LIU, TYM ;
CHIN, GM ;
JEON, DY ;
MORRIS, MD ;
ARCHER, VD ;
JOHNSON, RW ;
TARSIA, M ;
KIM, HH ;
CERULLO, M ;
LEE, KF ;
SUNG, JMJ ;
LAU, KS ;
CHIU, TY ;
VOSHCHENKOV, AM ;
SWARTZ, RG .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (09) :1546-1555
[7]  
Nambu H., 1991, 1991 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.91CH3018-9), P11, DOI 10.1109/VLSIC.1991.760054
[8]  
Shiba T., 1991, International Electron Devices Meeting 1991. Technical Digest (Cat. No.91CH3075-9), P455, DOI 10.1109/IEDM.1991.235357
[9]  
SHIBA T, 1993, PROCEEDINGS OF THE 1993 BIPOLAR/BICOMS CIRCUITS AND TECHNOLOGY MEETING, P67, DOI 10.1109/BIPOL.1993.617471
[10]   ADVANCED PROCESS DEVICE TECHNOLOGY FOR O.3-MU-M HIGH-PERFORMANCE BIPOLAR LSIS [J].
TAMAKI, Y ;
SHIBA, T ;
KURE, T ;
OHYU, K ;
NAKAMURA, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (06) :1387-1391