ADVANCED PROCESS DEVICE TECHNOLOGY FOR O.3-MU-M HIGH-PERFORMANCE BIPOLAR LSIS

A new method is developed for forming a shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-mu-m bipolar LSI's. Fabricated 0.5-mu-m U-SICOS (U-groove isolated Sidewall base Contact Structure) transistors are 44-mu-m2, and they have an isolation width of 2.0-mu-m, a minimum emitter width of 0.2-mu-m, a maximum cutoff frequency (f(T)) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-mu-m bipolar LSI's are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f(T) and base resistance is also discussed.