On-chip synchronous detection for CMOS BDJ optical detector

On-chip electronics performing weak-signal recovery for CMOS BDJ (Buried Double p-n Junction) optical detector is proposed. It includes two identical channels for simultaneous processing of both detector's output signals in continuous-time configuration. Each channel consists of a transimpedance amplifier, a fully differential amplifier, a multiplier and a low-pass filter, thus performing low-noise preamplification and synchronous demodulation. Some key building blocks have been designed with performance optimisation. In order to validate the proposed architecture, to verify the system operation and to estimate its performances and characteristics, system-level simulations have been carried out. It has been evaluated that, in a typical case, the integrated system can detect an input optical signal of 21 fW/mm(2).