Electrical stressing effects in commercial power VDMOSFETs

The effects of DC gate bias stressing on threshold voltage and channel carrier mobility in commercial power VDMOSFETs from two different manufacturers are studied. Underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. Apart from certain quantitative differences, it is shown that gate bias stressing has qualitatively the same effects and causes significant threshold voltage shift and mobility degradation in both VDMOS devices. Negative gate bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger after stressing by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon =Si-o(center dot) defects into the oxide conduction band and subsequent hole tunnelling from the charged oxide traps =Si-o(+) to interface-trap precursors =Si-s-H are proposed to be the main mechanisms responsible for build-up of positive oxide-trapped charge and interface traps, respectively. In the case of negative bias stressing, hole tunnelling from, the silicon valence band to oxygen vacancy defects =(SioSio)-Si-center dot center dot= is shown to be responsible for build-up of oxide-trapped charge, and subsequent electro-chemical reactions of interfacial precursors =Si-s-H with charged oxide traps =Si-o(+)center dot Si-o= and H+ ions for that of interface traps.