A noise optimization technique for integrated low-noise amplifiers

被引：82

作者：

Goo, JS ^{[1
]}

Ahn, HT

Ladwig, DJ

Yu, ZP

Lee, TH

Dutton, RW

机构：

[1] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA

[2] Qualcomm, San Diego, CA 92121 USA

[3] Texas Instruments Inc, Dallas, TX 75243 USA

[4] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2002年 / 37卷 / 08期

关键词：

amplifier noise; induced gate noise; low-noise amplifier; microwave amplifier; MOSFET amplifier; noise figure; random noise; semiconductor device noise;

D O I：

10.1109/JSSC.2002.800956

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NFmin by choosing an appropriate device geometry along with an optimal bias condition. An 800-MHz LNA has been implemented in a standard 0.24-mum CMOS technology. The amplifier possesses a 0.9-dB noise figure with a 7.1-dBm third-order input intercept point, while drawing 7.5 mW from a 2.0-V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

引用

页码：994 / 1002

页数：9

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