Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive

被引：32

作者：

Ionescu, AM ^{[1
]}

Mahapatra, S ^{[1
]}

Pott, V ^{[1
]}

机构：

[1] Swiss Fed Inst Technol, EPFL, IMM, Elect Lab,LEG, CH-1015 Lausanne, Switzerland

来源：

IEEE ELECTRON DEVICE LETTERS | 2004年 / 25卷 / 06期

关键词：

circuit simulation; CMOS-SET hybrid technology; negative differential resistance (NDR) device; semiconductor device model; single electron transistor (SET);

D O I：

10.1109/LED.2004.828558

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel hybrid single electron transistor/MOSFET (SETMOS) circuit cell architecture, working as a three-terminal stand-alone device for obtaining SET-like Coulomb Blockade oscillations, along with a high current drive (similar to muA), is proposed. SETMOS characteristics are successfully predicted by analytical models at subambient (-100 degreesC to -150 degreesC) temperature with realistic device parameters. The effect of bias voltages and current on the SETMOS Coulomb Blockade oscillations characteristics is critically discussed. It is also demonstrated that the SETMOS can be converted into a unique quasi-periodic negative differential resistance (NDR) device by short-circuiting its gate and drain terminals.

引用

页码：411 / 413

页数：3

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