Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks

被引:24
作者
Wang, ZG [1 ]
Parker, CG [1 ]
Hodge, DW [1 ]
Croswell, RT [1 ]
Yang, N [1 ]
Misra, V [1 ]
Hauser, JR [1 ]
机构
[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA
关键词
Fermi level; flatband voltage; interface; ON;
D O I
10.1109/55.830971
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we demonstrate that the magnitude of flatband voltage (V-FB) Shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's depends on the Fermi level position in the gate material. Tn addition, a fixed positive charge at the oxide-nitride interface was observed.
引用
收藏
页码:170 / 172
页数:3
相关论文
共 8 条
[1]  
Hauser JR, 1998, AIP CONF PROC, V449, P235
[2]  
MA Y, 1999, P EL SOC 195 M SEATT
[3]   Interfacial properties of ultrathin pure silicon nitride formed by remote plasma enhanced chemical vapor deposition [J].
Misra, V ;
Lazar, H ;
Wang, Z ;
Wu, Y ;
Niimi, H ;
Lucovsky, G ;
Wortman, JJ ;
Hauser, JR .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1999, 17 (04) :1836-1839
[4]   Ultrathin oxide-nitride gate dielectric MOSFET's [J].
Parker, CG ;
Lucovsky, G ;
Hauser, JR .
IEEE ELECTRON DEVICE LETTERS, 1998, 19 (04) :106-108
[5]   Carrier recombination at silicon-silicon nitride interfaces fabricated by plasma-enhanced chemical vapor deposition [J].
Schmidt, J ;
Aberle, AG .
JOURNAL OF APPLIED PHYSICS, 1999, 85 (07) :3626-3633
[6]   Observation of multiple defect states at silicon silicon nitride interfaces fabricated by low-frequency plasma-enhanced chemical vapor deposition [J].
Schmidt, J ;
Schuurmans, FM ;
Sinke, WC ;
Glunz, SW ;
Aberle, AG .
APPLIED PHYSICS LETTERS, 1997, 71 (02) :252-254
[7]   SHALLOW-JUNCTION FORMATION ON SILICON BY RAPID THERMAL-DIFFUSION OF IMPURITIES FROM A SPIN-ON SOURCE [J].
USAMI, A ;
ANDO, M ;
TSUNEKANE, M ;
WADA, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (01) :105-110
[8]   Ultrathin nitride/oxide (N/O) gate dielectrics for p+-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD thermal oxidation process [J].
Wu, YD ;
Lucovsky, G .
IEEE ELECTRON DEVICE LETTERS, 1998, 19 (10) :367-369