Planar and vertical double gate concepts

被引：25

作者：

Schulz, T ^{[1
]}

Rösner, W

Landgraf, E

Risch, L

Langmann, U

机构：

[1] Infineon Technol AG, Corp Res, D-81730 Munich, Germany

[2] Ruhr Univ Bochum, D-44780 Bochum, Germany

来源：

SOLID-STATE ELECTRONICS | 2002年 / 46卷 / 07期

关键词：

MOSFET; vertical; double gate; SOI; lithography independent; nanoscale;

D O I：

10.1016/S0038-1101(02)00031-X

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we report a comparative study of different double gate architectures. The main focus is on the fabrication method of two different device concepts developed in our group. The first is a planar version with special SOI wafers or deposited films and the second is a vertical transistor with lithography independent channel length. In addition to a thorough structural analysis we present electrical characteristics of the fabricated devices. (C) 2002 Elsevier Science Ltd. All rights reserved.

引用

页码：985 / 989

页数：5

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