The mechanism of mobility degradation in MISFETs with Al2O3 gate dielectric

We believe that the most important task in the development of high-kappa gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, AlO3, would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al2O3, gate dielectrics in sub-100 nm-FETs has already' been demonstrated [1]; however, the resulting electron mobility was only a quarter the value for a FET with SiO2 gate dielectric [1,2]. We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.