Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

被引：217

作者：

Rim, K ^{[1
]}

Chu, J ^{[1
]}

Chen, H ^{[1
]}

Jenkins, KA ^{[1
]}

Kanarsky, T ^{[1
]}

Lee, K ^{[1
]}

Mocuta, A ^{[1
]}

Zhu, H ^{[1
]}

Roy, R ^{[1
]}

Newbury, J ^{[1
]}

Ott, J ^{[1
]}

Petrarca, K ^{[1
]}

Mooney, P ^{[1
]}

Lacey, D ^{[1
]}

Koester, S ^{[1
]}

Chan, K ^{[1
]}

Boyd, D ^{[1
]}

Leong, M ^{[1
]}

Wong, HS ^{[1
]}

机构：

[1] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015406

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled V-T and C-ov characteristics for L-poly and L-eff below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

引用

页码：98 / 99

页数：2

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