Complementary symmetry silicon nanowire logic: Power-efficient inverters with gain

The investigation and preparation of silicon nanowire (NW) and microwire n- and p-Field Effect Transistors (p-FETs) are described. The features of complementary NW devices including p-type Si / n-type Si or GaN hetero junctions for diode logic, are also reported. These logic gates are better than those structures based on pure p- or n-type technology. These systems are limited by both the stochastic chemical nature of the NW formation and doping. A suitable technique for combining both p- and n-type NWs within a single, ultra high-density, highly aligned NW array is presented. Four types of devices are characterized and compared namely NW p- and n-FETs and μW p- and n-FETs. A systematic study of the dopant concentrations are carried out for the fabrication of the NW. A complementary inverter involves a p-FTE and n-FET in series with a shared contact as output. The surface sensitivity of Si NW FETs is used to develop ultra high density Si NW arrays.