Phosphorus pileup and sublimation at the silicon surface

被引：11

作者：

Sato, Y ^{[1
]}

Imai, K ^{[1
]}

Yabumoto, N ^{[1
]}

机构：

[1] NTT ADV TECHNOL INC, ATSUGI, KANAGAWA 24301, JAPAN

来源：

JOURNAL OF THE ELECTROCHEMICAL SOCIETY | 1997年 / 144卷 / 07期

关键词：

D O I：

10.1149/1.1837853

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Low-dose implanted phosphorus that escapes from silicon to pile up at and/or sublimate through the silicon surface during rapid thermal annealing was investigated. Phosphorus-implanted (100) silicon wafers were piranha-cleaned or the BHF-etched, and then annealed at 800 to 1000 degrees C for up to 180 s in nitrogen. Phosphorus sublimation was observed for the BHF-etched wafers at 800 degrees C and the piranha-cleaned wafers at 1000 degrees C. Phosphorus pileup was observed for both types of wafers.

引用

页码：2548 / 2551

页数：4

共 11 条

[1] VACANCY SUPERSATURATION IN SI UNDER SIO2 CAUSED BY SIO FORMATION DURING ANNEALING IN AR [J].