Low-Threshold-Voltage MoN/HfAlO/SiON p-MOSFETs With 0.85-nm EOT

被引：13

作者：

Chang, M. F. ^{[1
,2
]}

Lee, P. T. ^{[1
,2
]}

Chin, Albert ^{[3
,4
]}

机构：

[1] Natl Chiao Tung Univ, Dept Photon, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Inst Electopt Engn, Hsinchu 300, Taiwan

[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[4] Nanoelect Consortium Taiwan, Hsinchu 300, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 08期

关键词：

Capping layer; HfAlO; MoN; p-MOSFETs; METAL-GATE; WORK-FUNCTION; CMOS; TECHNOLOGY;

D O I：

10.1109/LED.2009.2023824

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

By using HfAlO as a capping layer on SiON, MoN/HfAlO/SiON p-MOSFETs show an effective work function of 5.1 eV, a low threshold voltage of -0.1 V, and a peak hole mobility of 80 cm(2)/(V . s) at small equivalent oxide thickness of 0.85 nm. These self-aligned and gate-first p-MOSFETs processes, with standard ion implantation and 1000 degrees C rapid thermal annealing, are fully compatible with current very large scale integration fabrication lines.

引用

页码：861 / 863

页数：3

共 17 条

[1] VFB roll-off in HfO2 gate stack after high temperature annealing process -: A crucial role of out-diffused oxygen from HfO2 to Si [J].

Akiyama, K. ;

Wang, W. ;

Mizubayashi, W. ;

Ikeda, M. ;

Ota, H. ;

Nabatame, T. ;

Toriumi, A. .

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :72-+

[2] Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions [J].

Cheng, C. F. ;

Wu, C. H. ;

Su, N. C. ;

Wang, S. J. ;

McAlister, S. P. ;

Chin, Albert .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :333-+

[3]

Chin A., 1999, VLSI Technology, Digest of Technical Papers, P135

[4]

HAUSER J, 2000, CVC NCSU SOFTWARE VE

[5]

HSU PF, 2006, VLSI S, P11

[6]

Huang J, 2008, INT EL DEVICES MEET, P45

[7]

*INT TECHN ROADM S, 2007, PROC INT DEV STRUCT, P11

[8] Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 mn LSTP utilizing process-friendly TiAlN metal gate [J].

Kadoshima, M. ;

Matsuki, T. ;

Sato, M. ;

Aminaka, T. ;

Kurosawa, E. ;

Ohta, A. ;

Yoshinaga, H. ;

Miyazaki, S. ;

Shiraishi, K. ;

Yamabe, K. ;

Yamada, K. ;

Aoyama, T. ;

Nara, Y. ;

Ohji, Y. .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :531-+

[9]

LEE KL, 2006, VLSI S, P160

[10]

LIAO CC, 2008, S VLSI, P190

← 1 2 →