A single-chip fingerprint sensor and identifier

被引:56
作者
Shigematsu, S [1 ]
Morimura, H
Tanabe, Y
Adachi, T
Machida, K
机构
[1] Nippon Telegraph & Tel Corp, Lifestyle & Environm Technol Labs, Atsugi, Kanagawa 2430198, Japan
[2] Nippon Telegraph & Tel Corp, Telecommun Energy Labs, Atsugi, Kanagawa 2430198, Japan
关键词
biometrics sensors; fingerprint identification; fingerprint sensor; image processing; pixel-parallel processing; smart pixel;
D O I
10.1109/4.808910
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A chip architecture that integrates a fingerprint sensor and an identifier in a single chip is proposed. The fingerprint identifier is formed by an array of pixels, and each pixel contains a sensing element and a processing element. The sensing element senses capacitances formed by a finger surface to capture a fingerprint image. An identification is performed by the pixel-parallel processing of the pixels. The sensing element is built above the processing element in each pixel. The chip architecture realizes a wide-area sensor without a large increase of chip size and ensures high sensor sensitivity while maintaining a high image density. The sensing element is covered with a hard film to prevent physical and chemical degradation and surrounded by a ground wall to shield it. The wall is also exposed on the chip surface to protect against damage by electrostatic discharges from the finger contacting the chip. A 15 x 15 mm(2) single-chip fingerprint sensor/identifier LSI was fabricated using 0.5-mu m standard CMOS with the sensor process. The sensor area is 10.1 x 13.5 mm(2). The sensing and identification time is 102 ms with power consumption of 8.8 mW at 3.3 V. Five hundred tests confirmed a stranger-rejection rate of the chip of more than 99% and a user-rejection rate of less than 1%.
引用
收藏
页码:1852 / 1859
页数:8
相关论文
共 16 条
[1]   Camera on a chip [J].
Ackland, B ;
Dickinson, A .
1996 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 1996, 39 :22-25
[2]   A 0.8-mu m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage [J].
DominguezCastro, R ;
Espejo, S ;
RodriguezVazquez, A ;
Carmona, RA ;
Foldesy, P ;
Zarandy, A ;
Szolgay, P ;
Sziranyi, T ;
Roska, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (07) :1013-1026
[3]  
INGLIS C, 1998, ISSCC FEB, P284
[4]   A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector [J].
Jiang, HC ;
Wu, CY .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (02) :241-247
[5]   A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras [J].
Kawahito, S ;
Yoshida, M ;
Sasaki, M ;
Umehara, K ;
Miyazaki, D ;
Tadokoro, Y ;
Murata, K ;
Doushou, S ;
Matsuzawa, A .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (12) :2030-2041
[6]  
KNAPP AG, 1994, Patent No. 5325442
[7]  
KOBAYASHI T, 1992, P 4 INT C COMP INF, P341
[8]   A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique [J].
Lee, JW ;
Min, DJ ;
Kim, J ;
Kim, W .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (04) :469-475
[9]   A 200-mW, 3.3-V, CMOS color camera IC producing 352x288 24-b video at 30 frames/s [J].
Loinaz, MJ ;
Singh, KJ ;
Blanksby, AJ ;
Inglis, DA ;
Azadet, K ;
Ackland, BD .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :2092-2103
[10]  
Morimura H., 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326), P157, DOI 10.1109/VLSIC.1999.797269