Accurate analytical delay expression for short channel CMOS SOI inverter using Monte Carlo simulation

被引:1
作者
Galdin, S [1 ]
Arbey, ME [1 ]
Dollfus, P [1 ]
Hesto, P [1 ]
机构
[1] Univ Paris 11, Inst Elect Fondamentale, CNRS UMR 8622, F-91405 Orsay, France
关键词
D O I
10.1016/S0038-1101(99)00147-1
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This payer reports on an analysis of propagation delay tau(D) for deep sub-micron CMOS/SOI inverters. We derive simple propagation delay expressions for step and ramp inputs, using Monte Carlo simulation. These expressions consist of linear combinations of time constants. As a physical device simulation tool, the Monte Carlo method is well adapted to such a study, since it does not require any analytical model of electrical device parameters. The validity of the above expressions is critically checked via Monte Carlo simulation of a wide range of inverters under various load conditions. The discrepancy between calculated and simulated propagation delay is less than 10%. (C) 1999 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:1869 / 1877
页数:9
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