Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices

被引：89

作者：

Bisdounis, L ^{[1
]}

Nikolaidis, S

Koufopavlou, O

机构：

[1] Univ Patras, Dept Elect & Comp Engn, VLSI Design Lab, Patras 26500, Greece

[2] Aristotelian Univ Salonika, Dept Phys, Elect & Comp Div, GR-54006 Salonika, Greece

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 02期

关键词：

circuit transient analysis; delay effects; delay estimation; inverters; short-channel MOSFET's;

D O I：

10.1109/4.658636

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper an accurate, analytical model for the evaluation of the CMOS inverter transient response and propagation delay for short-channel devices is presented. An exhaustive analysis of the inverter operation is provided which results in accurate expressions of the output response to an input ramp. Most of the factors which influence the inverter operation are taken into account. The alpha-power law MOS model, which considers the carriers' velocity saturation effects of short-channel devices, is used, The final results are in excellent agreement with SPICE simulations.

引用

页码：302 / 306

页数：5

共 13 条

[1]

BURNS JR, 1964, RCA REV, V25, P627

[2] A COMPREHENSIVE DELAY MODEL FOR CMOS INVERTERS [J].

DUTTA, S ;

SHETTI, SSM ;

LUSKY, SL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (08) :864-871

[3] DELAY MODELS FOR CMOS, BICMOS AND BINMOS CIRCUITS AND THEIR APPLICATIONS FOR TIMING SIMULATIONS [J].

EMBABI, SHK ;

DAMODARAN, R .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (09) :1132-1142

[4] CMOS CIRCUIT SPEED AND BUFFER OPTIMIZATION [J].

HEDENSTIERNA, N ;

JEPPSON, KO .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (02) :270-281

[5] MODELING THE INFLUENCE OF THE TRANSISTOR GAIN RATIO AND THE INPUT-TO-OUTPUT COUPLING CAPACITANCE ON THE CMOS INVERTER DELAY [J].

JEPPSON, KO .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (06) :646-654

[6] ANALYTICAL TRANSIENT-RESPONSE OF CMOS INVERTERS [J].

KAYSSI, AI ;

SAKALLAH, KA ;

BURKS, TM .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1992, 39 (01) :42-44

[7] INVERTER MODELS OF CMOS GATES FOR SUPPLY CURRENT AND DELAY EVALUATION [J].

NABAVILISHI, A ;

RUMIN, NC .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (10) :1271-1279

[8] SIMULTANEOUS DELAY AND MAXIMUM CURRENT CALCULATION IN CMOS GATES [J].

NABAVILISHI, A ;

RUMIN, NC .

ELECTRONICS LETTERS, 1992, 28 (07) :682-684

[9] ALPHA-POWER LAW MOSFET MODEL AND ITS APPLICATIONS TO CMOS INVERTER DELAY AND OTHER FORMULAS [J].

SAKURAI, T ;

NEWTON, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (02) :584-594

[10] DELAY ANALYSIS OF SERIES-CONNECTED MOSFET CIRCUITS [J].

SAKURAI, T ;

NEWTON, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (02) :122-131

← 1 2 →