Self-aligned surface tunnel transistors fabricated by a regrowth technique

A self-aligned process for fabricating surface tunnel transistors (STTs) has been developed in an attempt to improve both miniaturization and integration of STTs. In this process, the keys to obtaining a flat regrown layer and fine tunnel junctions are to keep from contaminating the surface during the lithography process before regrowth and to control the side-wall profile of the gate region in which tunnel junctions are formed. The carbon contamination can be reduced significantly by using a double hard mask consisting of Si3N4 and SiO2, and oxygen contamination can be removed by atomic hydrogen irradiation. The side-wall profile, that is etched surface morphology and side-wall angle, can be optimized by adjusting the composition of the H3PO4:H2O2:H2O etching solution. During regrowth, a flat surface morphology and fine tunnel junctions were obtained at the low temperature of 400 degrees C. Self-aligned InGaAs-based STTs with gate-controlled negative differential resistance (NDR) characteristics showing a peak-to-valley (P/V) ratio of 2.5 were obtained.