Fabrication and comparison of ferroelectric capacitor structures for memory applications

Ferroelectric capacitors of Pt/PbZrxTi1-xO3/Pt system were integrated to examine the various capacitor structures. Three test structures of PZT capacitors were chosen for the fabrication and comparison. These were classified by how the capacitor area was defined and whether the sacrificial area of PZT film existed. Process integration includes back-end processing as well as ferroelectric processing. PZT and Pt thin films were prepared by metallo-organic decomposition (MOD) and DC magnetron sputtering, respectively. TiO2 was employed as a reaction barrier layer between PZT and SiO2 interlayer dielectric layer. Process flows for the fabrication of test capacitors have been developed for the device integration. Finally, the test structures of PZT capacitors were evaluated in terms of the electrical properties of the capacitors including hysteresis loop, fatigue, and leakage current as well as process integration.