Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication

被引:104
作者
Liu, Yongxun [1 ]
Kijima, Shinya
Sugimata, Etsuro
Masahara, Meishoku
Endo, Kazuhiko
Matsukawa, Takashi
Ishii, Kenichi
Sakamoto, Kunihiro
Sekigawa, Toshihiro
Yamauchi, Hiromi
Takanashi, Yoshifumi
Suzuki, Eiichi
机构
[1] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki 3058568, Japan
[2] Tokyo Univ Sci, Noda, Chiba 278, Japan
关键词
double-gate MOSFET; FinFET; metal gate; tiNgate; work function;
D O I
10.1109/TNANO.2006.885035
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phi(TiN)) slightly decreases with increasing nitrogen (N-2) gas flow ratio, R-N = N-2/(Ar + N-2) in the sputtering, from 17% to 100%. The experimental threshold voltage (V-th) dependence on the R-N shows that the more R-N offers the lower V-th for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different R-N showed that the more amount of nitrogen is introduced into the TiN films with increasing R-N, which suggests that the lowering of phi(TiN) with increasing R-N, should be related to the increase in nitrogen concentration in the TiN film. The desirable V-th shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n(+) poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TIN gate FinFET fabrication.
引用
收藏
页码:723 / 730
页数:8
相关论文
共 34 条
[1]  
Choi Y. K., 2001, IEDM, P421
[2]  
Choi YK, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P259, DOI 10.1109/IEDM.2002.1175827
[3]  
Collaert N, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P108
[4]   High-performance p-type independent-gate FinFETs [J].
Fried, DM ;
Duster, JS ;
Kornegay, KT .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (04) :199-201
[5]   Improved independent gate N-type FinFET fabrication and characterization [J].
Fried, DM ;
Duster, JS ;
Kornegay, KT .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (09) :592-594
[6]   Molybdenum-gate HfO2CMOS FinFET technology [J].
Ha, DW ;
Takeuchi, H ;
Choi, YK ;
King, TJ ;
Bai, WP ;
Kwong, DL ;
Agarwal, A ;
Ameen, M .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :643-646
[7]   Poly-gate replacement through contact hole (PRETCH): A new method for high-K/metal gate and multi-oxide implementation on chip [J].
Harrison, S ;
Coronel, P ;
Cros, A ;
Cerutti, R ;
Leverd, F ;
Beverina, A ;
Wacquez, R ;
Bustos, J ;
Delille, D ;
Tavel, B ;
Barge, D ;
Bienacel, J ;
Samson, M ;
Martin, F ;
Maitrejean, S ;
Munteanu, D ;
Autran, JL ;
Skotnicki, T .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :291-294
[8]  
Hisamoto D., 1989, International Electron Devices Meeting 1989. Technical Digest (Cat. No.89CH2637-7), P833, DOI 10.1109/IEDM.1989.74182
[9]   A folded-channel MOSFET for deep-sub-tenth micron era [J].
Hisamoto, D ;
Lee, WC ;
Kedzierski, J ;
Anderson, E ;
Takeuchi, H ;
Asano, K ;
King, TJ ;
Bokor, J ;
Hu, CM .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :1032-1034
[10]   Feasibility of using W/TiN as metal gate for conventional 0.13μm CMOS technology and beyond [J].
Hu, JC ;
Yang, H ;
Kraft, R ;
Rotondaro, ALP ;
Hattangady, S ;
Lee, WW ;
Chapman, RA ;
Chao, CP ;
Chatterjee, A ;
Hanratty, M ;
Rodder, M ;
Chen, IC .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :825-828