Negative bias temperature stress on low voltage p-channel DMOS transistors and the role of nitrogen

被引:21
作者
Gamerith, S [1 ]
Pölzl, M [1 ]
机构
[1] Infineon Technol Austria, Microelect Design Ctr, A-9500 Villach, Austria
关键词
D O I
10.1016/S0026-2714(02)00165-8
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The instability of MOS devices under negative-bias temperature stress (NBTS) conditions is known to cause the buildup of fixed positive oxide charge Q(f) and interface traps Q(it). The power-law time dependence of this build up has been described theoretically by a diffusion-reaction model introduced by Jeppson and Svensson [1]. In this work we show that the model can be used to explain the degradation of the transfer characteristics of a new, low voltage, vertical power DMOS technology. Various process steps were analyzed in view of their impact on the NBTS behavior. The results indicate that nitrogen, introduced into the MOS system during a long-time, high-temperature diffusion step, plays the key role in the NBTS characteristics. Finally ways of improving NBTS hardness are proposed. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:1439 / 1443
页数:5
相关论文
共 17 条
[1]  
Balk P., 1988, SI SIO2 SYSTEM
[2]   MECHANISM OF NEGATIVE-BIAS-TEMPERATURE INSTABILITY [J].
BLAT, CE ;
NICOLLIAN, EH ;
POINDEXTER, EH .
JOURNAL OF APPLIED PHYSICS, 1991, 69 (03) :1712-1720
[3]   Bias temperature reliability of p-channel high-voltage devices [J].
Demesmaeker, A ;
Pergoot, A ;
DePauw, P .
MICROELECTRONICS AND RELIABILITY, 1997, 37 (10-11) :1767-1770
[4]  
DIMMITRIJEV S, 1989, SOLID STATE ELECT, V30, P991
[5]   Charge-pumping characterization of SiO2/Si interface in virgin and irradiated power VDMOSFETs [J].
Habas, P ;
Prijic, Z ;
Pantic, D ;
Stojadinovic, ND .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (12) :2197-2209
[6]   INTERFACE STATE GENERATION UNDER LONG-TERM POSITIVE-BIAS TEMPERATURE STRESS FOR A P+ POLY GATE MOS STRUCTURE [J].
HIRUTA, Y ;
IWAI, H ;
MATSUOKA, F ;
HAMA, K ;
MAEGUCHI, K ;
KANZAKI, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (09) :1732-1739
[7]   NEGATIVE BIAS STRESS OF MOS DEVICES AT HIGH ELECTRIC-FIELDS AND DEGRADATION OF MNOS DEVICES [J].
JEPPSON, KO ;
SVENSSON, CM .
JOURNAL OF APPLIED PHYSICS, 1977, 48 (05) :2004-2014
[8]   Lifetime prediction for PMOS, and NMOS devices based on a degradation model for Gate-Bias-stress [J].
Narr, A ;
Lill, A .
MICROELECTRONICS AND RELIABILITY, 1997, 37 (10-11) :1433-1436
[9]   GENERALIZED DIFFUSION-REACTION MODEL FOR THE LOW-FIELD CHARGE-BUILDUP INSTABILITY AT THE SI-SIO2 INTERFACE [J].
OGAWA, S ;
SHIONO, N .
PHYSICAL REVIEW B, 1995, 51 (07) :4218-4230
[10]   INTERFACE-TRAP GENERATION AT ULTRATHIN SIO2 (4-6NM)-SI INTERFACES DURING NEGATIVE-BIAS TEMPERATURE AGING [J].
OGAWA, S ;
SHIMAYA, M ;
SHIONO, N .
JOURNAL OF APPLIED PHYSICS, 1995, 77 (03) :1137-1148