1400V 4H-SiC power MOSFETs

被引:27
作者
Agarwal, AK [1 ]
Casady, JB [1 ]
Rowland, LB [1 ]
Valek, WF [1 ]
Brandt, CD [1 ]
机构
[1] Northrop Grumman Sci & Technol Ctr, Pittsburgh, PA 15235 USA
来源
SILICON CARBIDE, III-NITRIDES AND RELATED MATERIALS, PTS 1 AND 2 | 1998年 / 264-2卷
关键词
UMOS; power devices; high voltage; MOSFET;
D O I
10.4028/www.scientific.net/MSF.264-268.989
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Silicon Carbide (4H-SiC), power U-Metal-Oxide-Semiconductor Field-Effect Transistors (UMOSFETs) were fabricated and characterized from room temperature to 200 degrees C. The devices had a 12 mu m thick lightly doped n-type drift layer, and a nominal channel length of 4 mu m. When tested under Fluorinert(TM) at room temperature, blocking voltages ranged from 1.3 kV to 1.4 kV. Effective channel mobility ranged from 1.5 cm(2)/V.s at room temperature with a gate bias of 32 V (oxide field similar to 3.5 MV/cm) up to 7 cm(2)V.s at 100 degrees C with an applied gate bias of 26 V (oxide field similar to 2.9 MV/cm). Specific on-resistance (R-on,R-sp) was calculated to be as low as 74 m Omega.cm(2) at 100 degrees C under the same gate bias. Fowler-Nordheim measurements with positive gate bias on actual UMOS devices indicated thermionic field injection at elevated temperatures.
引用
收藏
页码:989 / 992
页数:4
相关论文
共 7 条
[1]   Critical materials, device design, performance and reliability issues in 4H-SiC power UMOSFET structures [J].
Agarwal, AK ;
Siergiej, RR ;
Seshadri, S ;
White, MH ;
McMullin, PG ;
Burk, AA ;
Rowland, LB ;
Brandt, CD ;
Hopkins, RH .
III-NITRIDE, SIC AND DIAMOND MATERIALS FOR ELECTRONIC DEVICES, 1996, 423 :87-92
[2]  
AGARWAL AK, 1997, UNPUB IEEE ELECT DEV
[3]   Silicon carbide MOSFET technology [J].
Brown, DM ;
Downey, E ;
Ghezzo, M ;
Kretchmer, J ;
Krishnamurthy, V ;
Hennessy, W ;
Michon, G .
SOLID-STATE ELECTRONICS, 1996, 39 (11) :1531-1542
[4]  
CHOW TC, COMMUNICATION
[5]  
PALMOUR JW, 1996, T 3 INT C HIGH TEMP, V2, P9
[6]   High-voltage double-implanted power MOSFET's in 6H-SiC [J].
Shenoy, JN ;
Cooper, JA ;
Melloch, MR .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (03) :93-95
[7]   CHARACTERIZATION AND OPTIMIZATION OF THE SIO2/SIC METAL-OXIDE-SEMICONDUCTOR INTERFACE [J].
SHENOY, JN ;
CHINDALORE, GL ;
MELLOCH, MR ;
COOPER, JA ;
PALMOUR, JW ;
IRVINE, KG .
JOURNAL OF ELECTRONIC MATERIALS, 1995, 24 (04) :303-309