A new model for the current factor mismatch in the MOS transistor

被引：14

作者：

Difrenza, R ^{[1
]}

Llinares, P

Ghibaudo, G

机构：

[1] STMicroelectronics, Cent R&D, F-38926 Crolles, France

[2] IMEP, ENSERG, F-38016 Grenoble, France

来源：

SOLID-STATE ELECTRONICS | 2003年 / 47卷 / 07期

关键词：

MOS transistor; matching; fluctuations; current factor; carrier mobility;

D O I：

10.1016/S0038-1101(03)00034-0

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 [电气工程]; 0809 [电子科学与技术];

摘要：

This paper presents a new model for the current factor mismatch of the MOS transistor. It demonstrates that the impact of interface states is negligible. Therefore, the analytical model is based on the random variations of the dopant number in the channel region, similarly to V, mismatch model. As a result, the theoretical value of the matching parameter A(beta) is 0.26% mum for NMOS and 0.51% mum for PMOS transistors that is close to experimental results. (C) 2003 Elsevier Science Ltd. All rights reserved.

引用

页码：1167 / 1171

页数：5

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