A CMOS technology platform for 0.13μm generation SOC(system on a chip)

被引：10

作者：

Yoshimura, H ^{[1
]}

Nakayama, T ^{[1
]}

Nishigohri, M ^{[1
]}

Inohara, M ^{[1
]}

Miyashita, K ^{[1
]}

Morifuji, E ^{[1
]}

Oishi, A ^{[1
]}

Kawashima, H ^{[1
]}

Habu, M ^{[1
]}

Koike, H ^{[1
]}

Takato, H ^{[1
]}

Toyoshima, Y ^{[1
]}

Ishiuchi, H ^{[1
]}

机构：

[1] Toshiba Corp, Microelect Engn Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852802

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we demonstrate a platform technology for 0.13 mu m generation SOC(system on a chip). 0.11 mu m LOGIC process with trench capacitor DRAM cell of 0.3 mu m(2) and 6Tr SRAM cell of 2.5 mu m(2) is described. Source/drain extensions are formed after deep junction activation by using disposable gate sidewalls. Thus ideal annealing condition is applied to source/drain extensions for shallow junction formation. In addition, second sidewalls for Co SALICIDE are optimized for suppression of boron penetration from p(+) poly-silicon gate.

引用

页码：144 / 145

页数：2

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