Power estimation and thermal budgeting methodology for FPGAs

被引：5

作者：

Lui, HY ^{[1
]}

Lee, CH ^{[1
]}

Patel, RH ^{[1
]}

机构：

[1] Altera Corp, San Jose, CA 95134 USA

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358928

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The method used for power estimation and thermal budgeting on an FPGA product line, which will be fabricated using the 90nm technology is described in this paper. It addresses the reasons why state-of-the-art processes create power concerns on FPGAs, and describes methodologies that provide more relevant power and junction temperature estimations. Finally it suggests what can be done to improve the power budget and to balance the trade-offs between power and performance.

引用

页码：711 / 714

页数：4

共 10 条

[1]

BORKER S, 2002, INT MICR RES FOR OCT

[2]

GEROGE V, 1999, INT S LOW OPW EL DES, P188

[3]

GEROUSIS V, 2003, P CICC

[4] Subthreshold leakage modeling and reduction techniques [J].

Kao, J ;

Narendra, S ;

Chandrakasan, A .

IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, :141-148

[5] Dynamic VTH Scaling scheme for active leakage power reduction [J].

Kim, CH ;

Roy, K .

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, :163-167

[6]

KUMAR R, 2002, P 15 INT C VLSI DES

[7] Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits [J].

Pant, P ;

Roy, RK ;

Chatterjee, A .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9 (02) :390-394

[8]

POON K, 2002, POWER ESTIMATION FIE

[9] Power-dissipation driven FPGA place and route under timing constraints [J].

Roy, K .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1999, 46 (05) :634-637

[10]

2001, POWER ANAL QUARTUS 2

← 1 →