A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies

被引:16
作者
Chatterjee, A [1 ]
Rodder, M [1 ]
Chen, IC [1 ]
机构
[1] Texas Instruments Inc, Semicond Proc & Device Ctr, Dallas, TX 75265 USA
关键词
CMOS; figure-of-merit; gate resistance; salicide; silicide;
D O I
10.1109/16.678526
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-mu m CMOS process, A furnace TiSi2 process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness.
引用
收藏
页码:1246 / 1252
页数:7
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