A FUNDAMENTAL PERFORMANCE LIMIT OF OPTIMIZED 3.3-V SUB-QUARTER-MICROMETER FULLY OVERLAPPED LDD MOSFETS

This paper reports the direct experimental quantification of the relationship between gate-to-drain capacitance (C(gd)) and hot-electron reliability (HER) for fully overlapped LDD (FOLD) n-channel MOSFET's (NFET's). To broaden the applicability and achieve a wide range of FOLD finger lengths, the results are based on devices built using each of three different fabrication techniques: 1) angled implant (AI)-FOLD, 2) inverse-T gate (IT)-FOLD, and 3) diffused (D)-FOLD. The experimentally observed tradeoff is compared to theoretical calculations to investigate its general and fundamental nature. Based on this tradeoff it is shown that a peak in performance occurs at L(eff) almost-equal-to 0.20-mu-m for reliable 3.3-V NFET's with T(ox) = 10 nm. Below 0.20-mu-m, performance decreases due to the addition of the large FOLD fingers required to maintain adequate hot electron reliability. This peak in performance can be shifted to L(eff) almost-equal-to 0.15-mu-m by introducing FOLD fingers only at the drain end of NFET's to form asymmetric FOLD NFET's. For channel lengths greater than 0.25-mu-m, it is found that the performance of 3.3-V FOLD NFET's and scaled 2.5-V single-diffusion NFET's are nearly equal. However, due to the 3.3-V NFET performance limit, 2.5-V single-diffusion NFET's begin to offer a significant performance advantage over 3.3-V FOLD NFET's as channel lengths are reduced below 0.25-mu-m.