CHOICE OF POWER-SUPPLY VOLTAGE FOR HALF-MICROMETER AND LOWER SUBMICROMETER CMOS DEVICES

Tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFET’s. Based upon physical understanding, the authors propose some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices, in order to maintain MOS device reliability and achieve high circuit performance. As a result, the authors have experimentally and semi-empirically clarified that power-supply voltage must be reduced to maintain reliability and improved performance, and further, the optimum voltage reduction follows the square root of the design rule. Moreover, trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7–45 nm) and gate lengths (0.3–2.0 µm). © 1990 IEEE