Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating

被引:34
作者
Dixit, Pradeep
Tan, Chee Wee
Xu, Luhua
Lin, Nay
Miao, Jianmin
Pang, John H. L.
Backus, Petra
Preisser, Robert
机构
[1] Nanyang Technol Univ, Micromachines Ctr, Sch Mech & Aerosp Engn, Singapore 639798, Singapore
[2] Atotech Deutschland GmbH, D-10553 Berlin, Germany
关键词
D O I
10.1088/0960-1317/17/5/030
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 [电气工程]; 0809 [电子科学与技术];
摘要
In this paper, we report the fabrication of high aspect ratio, highly dense, very fine pitch on-chip copper-pillar-based interconnects for advanced packaging applications. Photoresist molds up to a thickness of 80 mu m and having feature sizes as small as 5 mu m were fabricated using multi- step coating of the positive tone AZ9260 photoresist. Spin coating and lithography parameters were optimized to achieve smooth and vertical sidewalls. Copper interconnects having an aspect ratio up to 6 and a pitch size of 25 mu m were electroplated in the fabricated resist mold. Due to a very small pitch size, the total number of interconnects per cm(2) chip area is 160 000, which is much larger than the conventional solder- based interconnects. The electrical resistance of the electroplated copper interconnects was measured by 4-probe kelvin measurement configuration and was found to be in the range of 8 - 10 m Omega and the corresponding electrical resistivity was calculated as 2.4 mu Omega cm. Such low resistive interconnects can carry much larger electrical current without significant electrical loss, which is ideally suitable for next generation packaging applications. X-ray diffraction has shown the presence of the (220) texture along the length of electroplated copper pillars. Transmission electron microscope reveals the presence of nanoscale copper twins along the length of copper interconnects.
引用
收藏
页码:1078 / 1086
页数:9
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