Nanotechnology goals and challenges for electronic applications

被引:141
作者
Bohr, MT [1 ]
机构
[1] Intel Corp, Hillsboro, OR 97124 USA
关键词
carbon nanotube; complimentary metal-oxide-semiconductor (CMOS); dynamic random access memory (DRAM); logic; memory; metal-oxide-semiconductor (MOS); metal-oxide-semiconductor field-effect transistor (MOSFET); molecular electronics; nanotechnology; nanowire; scaling; single electron transistor; static random access memory (SRAM);
D O I
10.1109/TNANO.2002.1005426
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-mum generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs.
引用
收藏
页码:56 / 62
页数:7
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