A 0.13 μm poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

被引：5

作者：

Ponomarev, YV ^{[1
]}

Stolk, PA ^{[1
]}

Dachs, CJJ ^{[1
]}

Montree, AH ^{[1
]}

机构：

[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2000年 / 47卷 / 07期

关键词：

analog; CMOSFET's; MOS devices; poly-SiGe;

D O I：

10.1109/16.848300

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.

引用

页码：1507 / 1513

页数：7

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