Investigation into the scalability of selectively implanted buried subcollector (SIBS) for submicrometer InP DHBTs

Recent attempts to achieve 400 GHz or higher f(T) and f(MAX) with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tau(C) to be minimized without incurring a large total C-BC increase, and hence, a net improvement in f(T) and f(MAX) is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C-BC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f(T) and f(MAX). Parasitic resistances and high background doping limit the f(T) improvement, but the C-BC reduction is sufficient to demonstrate a 30% increase in f(MAX). Results indicate that further improvements in f(T) and f(MAX) using the SIBS concept will be possible.