Effect of grain boundaries on hot-carrier induced degradation in large grain polysilicon thin-film transistors

Hot-carrier effects have been investigated in n-channel thin-film transistors fabricated on large grain polysilicon films. The bias-stress conditions for maximum device degradation have been determined by photon emission measurements. Under these bias-stress conditions, devices with identical transfer characteristics before stress, are either stable or exhibit strong degradation with reduced field effect mobility. We propose that the different degradation behavior is related with the quality of the grain boundaries and their position in the channel with respect to the drain junction. The results indicate that when a grain boundary is located closer to the drain region, it becomes more prone to degradation by the hot carriers generated in the high field region of the drain junction. Numerical simulations suggest that the device degradation is due to an increase of the grain boundary band tail states. In addition to this mechanism, the existence of a critical path for the current flow from source to drain has been proposed to explain the observed different degradation behavior of similar devices. (C) 2000 Elsevier Science Ltd. All rights reserved.