Three-dimensional metal gate-high-κ-GOI CMOSFETs on 1-poly-6-metal 0.18-μm Si devices

被引:23
作者
Yu, DS [1 ]
Chin, A
Liao, CC
Lee, CF
Cheng, CF
Li, MF
Yoo, WJ
McAlister, SP
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Nano Sci Technol Ctr, Hsinchu 300, Taiwan
[2] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 119260, Singapore
[3] Natl Res Council Canada, Ottawa, ON K4C 1B6, Canada
关键词
Ge-on-insulator (GOI); LaAlO3; metal-gate; MOSFET; three-dimensional (3-D);
D O I
10.1109/LED.2004.841861
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.
引用
收藏
页码:118 / 120
页数:3
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