High hole and electron field effect mobilities in nanocrystalline silicon deposited at 150 °C

We demonstrate both p-channel and n-channel thin film transistors of nanocrystalline silicon (nc-Si:H) deposited at 150 degreesC. The TFTs are made in an inverted staggered top-gate bottom-source/drain geometry to place the channel in the last-to-grow layer, and to avoid plasma etch damage to the channel. The TFT structure is fabricated on top of a 75-mn thick intrinsic nc-Si:H seed layer, which serves to develop the crystalline structure of the channel layer. We obtained a hole mobility of similar to0.2 cm(2) V-1 s(-1) and an electron mobility of similar to40 cm(2) v(-1) s(-1). These results demonstrate the feasibility of a directly-deposited and CMOS capable silicon TFT technology on low-temperature substrates. (C) 2002 Elsevier Science B.V. All rights reserved.