Enhanced strain effects in 25-nm gate-length thin-body nMOSFETs with silicon-carbon source/drain and tensile-stress liner

被引:19
作者
Ang, Kah-Wee [1 ]
Chui, King-Jien
Tung, Chih-Hang
Balasubramanian, N.
Li, Ming-Fu
Samudra, Ganesh S.
Yeo, Yee-Chia
机构
[1] Natl Univ Singapore, Dept Elect & Comp Engn, SNDL, Singapore 119260, Singapore
[2] Inst Microelect, Singapore 117685, Singapore
关键词
electron mobility; nMOSFET; silicon-carbon (Si1-yCy); silicon nitride liner; strain; stress;
D O I
10.1109/LED.2007.893221
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report the demonstration of 25-nm gate-length L-G strained nMOSFETs featuring the silicon-carbon source and drain (Si1-yCyS/D) regions and a thin-body thickness T-body of similar to 18 nm. This is also the smallest reported planar nMOSFET with the Si1-yCyS/D stressors. Strain-induced mobility enhancement due to the Si1-yCyS/D leads to a significant drive-current I-Dsat enhancement of 52% over the control transistor. Furthermore, the integration of tensile-stress SiN etch stop layer and Si1-yCyS/D extends the I-Dsat enhancement to 67%. The performance enhancement was achieved for the devices with similar subthreshold swing and drain-induced barrier lowering. The Si1-yCyS/D technology and its combination with the existing strained-silicon techniques are promising for the future high-performance CMOS applications.
引用
收藏
页码:301 / 304
页数:4
相关论文
共 13 条
[1]  
Ang KW, 2005, INT EL DEVICES MEET, P503
[2]  
Ang KW, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P1069
[3]  
[Anonymous], 2003, IEEE INT ELECT DEVIC
[4]  
Ge CH, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P73
[5]   In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on (100), (110), and (111) Si [J].
Irie, H ;
Kita, K ;
Kyuno, K ;
Toriumi, A .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :225-228
[6]   Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design [J].
Ito, S ;
Namba, H ;
Yamaguchi, K ;
Hirata, T ;
Ando, K ;
Koyama, S ;
Kuroki, S ;
Ikezawa, N ;
Suzuki, T ;
Saitoh, T ;
Horiuchi, T .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :247-250
[7]  
LIOW JY, 2006, P S VLSI TECHN HON, P68
[8]   A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films [J].
Pidin, S ;
Mori, T ;
Inoue, K ;
Fukuta, S ;
Itoh, N ;
Mutoh, E ;
Ohkoshi, K ;
Nakamura, R ;
Kobayashi, K ;
Kawamura, K ;
Saiki, T ;
Fukuyama, S ;
Satoh, S ;
Kase, M ;
Hashimoto, K .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :213-216
[9]   Subband structure engineering for performance enhancement of Si MOSFETs [J].
Takagi, S ;
Koga, J ;
Toriumi, A .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :219-222
[10]  
Verheyen P, 2005, 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P194