A wideband sigma-delta phase locked-loop modulator for wireless application's

被引：16

作者：

Fahim, AA ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 2003年 / 50卷 / 02期

关键词：

digital; phase-locked loops (PLLs); Sigma-Delta; wireless;

D O I：

10.1109/TCSII.2003.809709

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A wideband phase-locked-loop (PLL) modulator for wireless applications is reported. This modulator is based on PLL fractional-N frequency synthesis techniques along with Sigma-Delta modulation to, randomize fractional-N spurs. A modified Sigma-Delta function allows for suppression of Sigma-Delta noise at lower frequencies, and hence allows for wider loop bandwidth. Also, Sigma-Delta quantization noise is reduced by using fractional division ratios. Low-power and low-area algorithmic techniques are used in the modified Sigma Delta modulator in order to make it a feasible option. It is shown that the resulting modulator meets the GSM specifications and has a total power consumption of 2 mW @ 1-GHz operation.

引用

页码：53 / 62

页数：10

共 20 条

[1]

AKIYAMA T, 1987, P IEEE S VLSI CIRC, P95

[2] A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-mu m CMOS [J].

Craninckx, J ;

Steyaert, MSJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (07) :890-897

[3]

Crawford J.A., 1994, FREQUENCY SYNTHESIZE

[4]

FILIOL N, 1993, IEEE J SOLID-ST CIRC, V28, P553

[5]

Fitzpatrick D., 1998, ANALOG BEHAV MODELIN

[6]

Koren I., 1993, COMPUTER ARITHMETIC

[7]

KWANG K, 1979, COMPUTER ARITHMETIC

[8]

MANASSEWITSCH M, 1980, FREQUENCY SYNTHESIZE

[9] A MULTIPLE MODULATOR FRACTIONAL DIVIDER [J].

MILLER, B ;

CONLEY, RJ .

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 1991, 40 (03) :578-583

[10]

MIZUNO M, 1992, P INT SOL STAT CIRC, P90

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