A 15-NS 4-MB CMOS SRAM

被引：8

作者：

AIZAKI, S ^{[1
]}

SHIMIZU, T ^{[1
]}

OHKAWA, M ^{[1
]}

ABE, K ^{[1
]}

AIZAKI, A ^{[1
]}

ANDO, M ^{[1
]}

KUDOH, O ^{[1
]}

SASAKI, I ^{[1
]}

机构：

[1] NEC IC MICROCOMP SYST LTD,KANAGAWA,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 05期

关键词：

D O I：

10.1109/4.62125

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 4-Mb SRAM, with a 15-ns access time and a uniquely selectable (x 4 or x 1) bit organization, has been developed based on a 0.55-μm triple-polysilicon double-metal CMOS technology. To achieve the access time of 15 ns, three key circuits, an input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCL’s), and a transfer word driver (TWD), have been utilized in addition to the 0.55-μm CMOS technology. Bit organization of either x4 or x1 can be selected purely electrically, and does not require any pin connection procedure. © 1990 IEEE

引用

页码：1063 / 1067

页数：5

共 6 条

[1]

HAYAKAWA S, 1988, AUG S VLSI CIRC, P53

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1060-1066

[3] A 25-NS 4-MBIT CMOS SRAM WITH DYNAMIC BIT-LINE LOADS [J].

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[4] A 9-NS 1-MBIT CMOS SRAM [J].

SASAKI, K ;

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1219-1225

[5] A 15-NS 1-MBIT CMOS SRAM [J].

SASAKI, K ;

HANAMURA, S ;

UEDA, K ;

OONO, T ;

MINATO, O ;

SAKAI, Y ;

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TSUNEMATSU, M ;

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KUBOTERA, M ;

TOYOSHIMA, H .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1067-1072

[6] AN 18-NS 1-MBIT CMOS SRAM [J].

SHIMADA, H ;

TANGE, Y ;

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SHIRAISHI, M ;

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NOMURA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1073-1077

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