A 14-NS 1-MBIT CMOS SRAM WITH VARIABLE BIT ORGANIZATION

被引:13
作者
KOHNO, Y
WADA, T
ANAMI, K
KAWAI, Y
YUZURIHA, K
MATSUKAWA, T
KAYANO, S
机构
关键词
D O I
10.1109/4.5925
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
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页码:1060 / 1066
页数:7
相关论文
共 10 条
[1]  
HONDA M, 1986, FEB ISSCC, P250
[2]   25-NS 256KX1/64KX4 CMOS SRAMS [J].
KAYANO, S ;
ICHINOSE, K ;
KOHNO, Y ;
SHINOHARA, H ;
ANAMI, K ;
MURAKAMI, S ;
WADA, T ;
KAWAI, Y ;
AKASAKA, Y .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) :686-691
[3]   A 35-NS 128KX8 CMOS SRAM [J].
KOMATSU, T ;
TANIGUCHI, H ;
OKAZAKI, N ;
NISHIHARA, T ;
KAYAMA, S ;
HOSHI, N ;
AOYAMA, JI ;
SHIMADA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :721-726
[4]   A RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE [J].
KUMANOYA, M ;
FUJISHIMA, K ;
MIYATAKE, H ;
NISHIMURA, Y ;
SAITO, K ;
MATSUKAWA, T ;
YOSHIHARA, T ;
NAKANO, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) :909-913
[5]   A 25-NS 1-MBIT CMOS SRAM WITH LOADING-FREE BIT LINES [J].
MATSUI, M ;
OHTANI, T ;
TSUJIMOTO, JI ;
IWAI, H ;
SUZUKI, A ;
SATO, K ;
ISOBE, M ;
HASHIMOTO, K ;
SAITOH, M ;
SHIBATA, H ;
SASAKI, H ;
MATSUNO, T ;
MATSUNAGA, JI ;
IIZUKA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :733-740
[6]  
MINATO O, 1987, FEB ISSCC, P260
[7]   A 34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON [J].
WADA, T ;
HIROSE, T ;
SHINOHARA, H ;
KAWAI, Y ;
YUZURIHA, K ;
KOHNO, Y ;
KAYANO, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :727-732
[8]  
WADA T, 1988, FEB ISSCC, P252
[9]   A 21-NS 32KX8 CMOS STATIC RAM WITH A SELECTIVELY PUMPED P-WELL ARRAY [J].
WANG, KL ;
BADER, MD ;
SOORHOLTZ, VW ;
MAUNTEL, RW ;
MENDEZ, HJ ;
VOSS, PH ;
KUNG, RI .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :704-711
[10]   A DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM [J].
YOSHIMOTO, M ;
ANAMI, K ;
SHINOHARA, H ;
YOSHIHARA, T ;
TAKAGI, H ;
NAGAO, S ;
KAYANO, S ;
NAKANO, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :479-485