NANOFABRICATION TECHNIQUES FOR 100 NM-SCALE SILICON METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

In this paper we report on an exploratory metal oxide semiconductor field effect transistor (MOSFET) device which we are currently investigating which requires 100 nm lithography at all critical levels to achieve a completely fully scaled 100 nm device structure. The device also incorporates a novel trench isolation scheme whereby the isolation trenches are etched after the gate electrodes have been formed leading to a butted gate configuration. The device further incorporates fully overlapped contacts to the gate, source, and drain regions in order to provide maximum contact area. We believe that this structure will provide a good basis for exploring the density and performance limits of 100 nm-scale devices. We describe here the structure of the proposed device and then we propose a suitable method of fabrication. This is followed by a demonstration of suitable nanofabrication techniques which are based, in each case, on high resolution electron beam lithography and precision reactive ion etching. Finally, we assess the feasibility of integrating these techniques in order to realize the proposed device.