ONO INTER-POLY DIELECTRIC SCALING FOR NONVOLATILE MEMORY APPLICATIONS

被引:44
作者
MORI, S [1 ]
SAKAGAMI, E [1 ]
ARAKI, H [1 ]
KANEKO, Y [1 ]
NARITA, K [1 ]
OHSHIMA, Y [1 ]
ARAI, N [1 ]
YOSHIKAWA, K [1 ]
机构
[1] TOSHIBA MICROELECTR CORP,SAIWAI KU,KAWASAKI 210,JAPAN
关键词
D O I
10.1109/16.69921
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The ONO (Oxide/Nitride/Oxide) inter-poly dielectric thickness scaling effect on E-I (electric field-leakage current) characteristics and charge retention characteristics in nonvolatile memories were investigated. Surface top-oxide thickness strongly affects the charge leakage and retention characteristics. Thicker than 3 nm top oxide can block hole injection from the anode. Thick top oxide can reduce leakage current in both high and low electric field regions. Moreover, it can improve charge retention characteristics in nonvolatile memory cells. Therefore, a certain amount of top oxide is required to preserve good charge retention characteristics. SiN thickness scaling leads to an improvement in charge retention characteristics. Bottom oxide has an important role in suppressing electron leakage in a low electric field region. A degraded quality thin bottom oxide leads to charge retention capability degradation. Therefore, bottom-oxide quality and thickness control is one of the most important subjects for ONO thickness scaling.
引用
收藏
页码:386 / 391
页数:6
相关论文
共 14 条
[1]   CONDUCTION AND CHARGE TRAPPING IN POLYSILICON-SILICON NITRIDE-OXIDE-SILICON STRUCTURES UNDER POSITIVE GATE BIAS [J].
AMINZADEH, M ;
NOZAKI, S ;
GIRIDHAR, RV .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (04) :459-467
[2]  
Bergemont A., 1989, International Electron Devices Meeting 1989. Technical Digest (Cat. No.89CH2637-7), P591, DOI 10.1109/IEDM.1989.74350
[3]   DOUBLE POLYSILICON PLATE CAPACITORS WITH OXIDE NITRIDE INSULATOR [J].
GILDENBLAT, G ;
GHEZZO, M ;
NORTON, J .
ELECTRONICS LETTERS, 1982, 18 (01) :34-36
[4]  
LIOU FT, 1984, IEEE T ELECTRON DEV, V31, P1736, DOI 10.1109/T-ED.1984.21780
[5]  
MIKATA Y, 1985, 1985 P IEEE IRPS, P32
[6]  
MORI S, 1989, AUG IEEE NONV SEM ME
[7]  
Mori S, 1984, VLSI S, P40
[8]  
MORI S, 1987, IEDM, P556
[9]  
Mori S, 1985, VLSI S, P16
[10]  
Mori S, 1986, VLSI S, P71