ION-IMPLANTED SUPER-GAIN TRANSISTORS

被引：10

作者：

GEGG, WM ^{[1
]}

SALTICH, JL ^{[1
]}

ROOP, RM ^{[1
]}

GEORGE, WL ^{[1
]}

机构：

[1] MOTOROLA INC,DIV INTEGRATED CIRCUIT,PHOENIX,AZ 85036

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1976年 / 11卷 / 04期

关键词：

D O I：

10.1109/JSSC.1976.1050763

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：485 / 491

页数：7

共 9 条

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[5] THE DEPENDENCE OF TRANSISTOR PARAMETERS ON THE DISTRIBUTION OF BASE LAYER RESISTIVITY [J].

MOLL, JL ;

ROSS, IM .

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[6]

PHILLIPS AB, 1962, TRANSISTOR ENGINEERI, P203

[7] USE OF SPECIFIC EMITTER EFFICIENCY IN EVALUATION AND DESIGN OF BIPOLAR TRANSISTORS [J].

SALTICH, JL ;

VOLK, CE ;

CLARK, LE .

PROCEEDINGS OF THE IEEE, 1973, 61 (05) :680-681

[8] DESIGN TECHNIQUES FOR MONOLITHIC OPERATIONAL AMPLIFIERS [J].

WIDLAR, RJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1969, SC 4 (04) :184-&

[9] SUPER-GAIN TRANSISTORS FOR ICS [J].

WIDLAR, RJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1969, SC 4 (04) :249-&

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