THERMAL-STRESS ANALYSIS OF SOIC PACKAGES AND INTERCONNECTIONS

被引：14

作者：

LAU, JH

HARKINS, CG

机构：

[1] Hewlett-Packard Lab, Palo Alto, CA,, USA

来源：

IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1988年 / 11卷 / 04期

关键词：

Integrated Circuits--Soldering - Mathematical Techniques--Finite Element Method - Soldering--Reliability - Stresses--Thermal;

D O I：

10.1109/33.16671

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Thermal stresses in surface-mounted small-outline integrated-circuit (SOIC) assemblies have been studied by the finite-element method. Emphasis is placed on the effects of solder-joint geometry on package and interconnection reliability. In addition, the problem of voids in solder joints is addressed. Seven different solder-joint geometries and six different sizes of voids are considered. It was found that the effect of voids in the solder joint is to increase the stresses acting on it. Furthermore, it is concluded that the results presented herein can provide guidelines for solder-joint inspection.

引用

页码：380 / 389

页数：10

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